This invention relates to multi-phase clock circuitry and, in particular, to an improved multiphase clock circuit in which the generation and propagation of clock pulse errors is contained and which clock circuit is highly suitable for use in combination with circuits (e.g., digital IQ mixer circuits) requiring multiphase clocks.
A clock signal in a digital circuit may consist of a periodic time series of pulses, at frequency fclock. In many digital circuits, two or more clock signals are required having the same frequencies but different phases. This can be obtained by shifting the pulses in a given clock signal relative to those in other clock signals by a fixed fraction of a clock period T=1/fclock. For example, if there are 4 clock signals of like frequency, the clocks are delayed relative to each other by T/4. That is, clock #2 is delayed from clock #1 by T/4, clock #3 is delayed from clock #2 by T/4, and clock #4 is delayed from clock #3 by T/4. These clock signals are typically identified in terms of phase delays, where a time T corresponds to a full clock cycle and a phase delay of 360 degrees. For a 4-phase clock, if clock #1 is defined as 0 degrees, clock #2 is 90 degrees, clock #3 is 180 degrees, and clock #4 is 270 degrees. The discussion above and to follow refers to a 4-phase clock; however, the number of phases of a multiphase clock may be equal to any number equal to, or greater than, 2.
Precision clocks are particularly critical for ultrafast superconducting circuits based on damped Josephson junctions, according to a logic family known as rapid-single-flux-quantum (RSFQ) logic. See, for example, U.S. Pat. No. 6,331,805, “On-chip long Josephson junction clock technology”. Simple RSFQ digital circuits such as a binary frequency divider (using toggle-flip-flops or TFFs) have been demonstrated at frequencies of several hundred gigahertz, faster than any other digital technology. More complex RSFQ digital integrated circuits have been operated at clock rates of 40 GHz or above.
Recently, a digital mixer circuit using a 4-phase clock of the type shown in FIG. 1A was demonstrated using RSFQ circuits, see U.S. patent application Ser. No. 11/243,019, publication #20070077906. FIG. 1A depicts a prior art multiphase clock circuit made up of a binary tree (divider circuit) using standard asynchronous RSFQ toggle-flip-flops with complementary output (TFFC cells). These cells can be interconnected to generate a clock with 2N equally-spaced phases, where N is the number of levels in the binary tree, and can be any number equal to or greater than one. In FIG. 1A, two (2) logic levels are shown; T1 forms the first logic level and T2 and T3 form the second logic level at which is produced four (4) clock outputs spaced 90 degrees apart from each other. Thus, FIG. 1A is a block diagram of a 2-stage prior art circuit that generates a 4-phase clock.
There is a subtle, but significant, problem/limitation associated with the circuit of the type shown in FIG. 1A which will be explained with reference to the detailed timing diagrams of FIGS. 1B and 1C.
The prior art circuit of FIG. 1A makes use of TFFCs which may be implemented using superconducting circuits which produce pulses (rather than voltage levels) at their outputs. The operation of a multiphase clock employing such TFFCs is illustrated in FIG. 1B. Assume a master clock source 11 produces a stream of pulses f0 into the input T1in (IN1) of TFFC T1, each pulse is directed alternately to the primary output T1out (O1) or to the complementary output T1Cout (O1C) (indicated in FIG. 1A by the small circle next to the output). The TFFC is an asynchronous element with a bistable internal latch that keeps track of the device history. A single TFFC may function as a two-phase clock, wherein a master clock source at f0 is split into two phase-coherent sources at f0/2, each 180 degrees out of phase with the other. If the outputs of this TFFC (e.g., T1) are directed to the inputs (e.g., IN2, IN3) of two other TFFCs (e.g., T2, T3), each of these (T2, T3) will produce another clock source at the rate of f0/4 at their respective outputs (e.g., O2, O2C, O3, O3C). These four outputs are phased at 0, 90, 180, and 270 degrees relative to one another.
The circuit of FIG. 1A is generally a highly reliable circuit; generating errors at a level which may typically be less than one part in a trillion (1012). However, although rare, an error may arise, such that an output pulse is directed to the “wrong” output, as indicated by the E in FIG. 1C. While the individual error events may be rare, in fast clocked systems, they dramatically limit the long-term proper functioning of the devices.
The nature of the problem with the circuit of FIG. 1A may be explained with reference to FIG. 1C which illustrates what happens when an error pulse occurs; e.g., a pulse that should have been directed to T1out is directed instead to T1Cout. Following the occurrence of the error, T1 directs its input pulses to alternating outputs, as it should. However, T1 continues to operate out of phase and supplies the out-of-phase signals to T2 and T3. The out-of-phase error is maintained within the system and does not reset to its initial phasal relationship. In the absence of an error pulse, the phasal relationships are defined as follows: the phase of T2out is at 0 degrees, T2Cout is 180 degrees, T3out is 90 degrees, and T3Cout is 270 degrees. After the occurrence of the error pulse, T2out still defines the 0 degrees phase and T2Cout is still 180 degrees, but T3out now corresponds to a phase which is displaced 270 degrees, and T3Cout now corresponds to a phase which is displaced 90 degrees from T2out. Two of the clock phases have switched and they subsequently remain switched, at least until another error occurs. In many applications of multiphase clocks, where the relative phases are critical, this results is a significant error.
The significance of the phasal-inversion errors discussed above was not recognized and understood. In fact, as shown in FIG. 6 and discussed below, the multiphase clock circuit of FIG. 1A was used as part of a digital local oscillator 60 in a digital IQ (in-phase and quadrature) mixer circuit in a digital radio receiver system. The FIG. 6 circuit demonstrated proper functionality in detailed simulation and low-speed testing. However, at high-speed operation, phase errors were generated, but the basis for such errors was not apparent. Only a careful re-analysis of error sources identified the problem. For example, if the master clock operates at f0=10 GHz (a typical value for high-speed RSFQ systems), then for a bit-error-rate of 10−12, an inversion error of this sort occurs once every 100 seconds. This is clearly unacceptable for proper long-term operation of the multiphase clock circuit.
Accordingly, Applicant's invention resides, in part, in the recognition that a multiphase clock circuit which allows for the propagation and regeneration or recirculation of error signals (uncorrected phasal switching) gives rise to potentially severe problems.
The erroneous operation present in the prior art circuit is not present in circuits embodying the invention which includes an improved (RSFQ) multiphase clock circuit which recovers automatically from rare bit errors, and also operates at high frequency with high clock precision.